In a memory subsystem of the computer system, if a physically tagged first level cache is used, the linear address (LA) generated by an address generation unit (AGU) may be translated into a physical address (PA). A translation look-aside buffer (TLB) may translate linear address to physical address. The TLB may comprise a plurality of entries and each entry may comprise a linear address and a corresponding physical address. The linear address generated may be compared with the entries in the TLB to generate a physical address. An increased size of the TLB may decrease the occurrence of TLB misses but, the increase in the size of the TLB may also decrease the speed at which the physical address is generated. It may be required to increase the size of the TLB while maintaining the speed of translation.